1. Field of the Invention
The present invention relates to a method of arranging and wiring cells having logical functions and to a semiconductor integrated circuit device based on the method.
2. Description of the Background Art
Standard cells have been prepared in advance on condition that the basic components needed for system design are standardized such as gates, flip-flops, functional blocks and that the layout design thereof is automated. Normally, the standard cells are defined by semiconductor-makers and are open to common users.
FIG. 12 is a plan view of the layout of a conventional integrated circuit in accordance with a standard cell system. Reference numeral 1 designates a power source wire, and 2 designates a grounding wire. There are provided cell rows 30 each including a plurality of standard cells 3 arranged in a predetermined direction (laterally in FIG. 12). Devices in the same standard cell 3 are connected to each other within the cell (as is not shown). Connection between the cells 3 is made such that an intercell signal wiring 6 (shown by the dotted lines of FIG. 12) is formed in an intercell signal wiring exclusive region 4 provided between the cell rows 30 to connect input/output terminals 5 (shown by the closed circles of FIG. 12) mounted in the respective standard cells 3 to each other through the intercell signal wiring 6.
In the conventional method of arranging and wiring cells in accordance with the standard cell system, all of the intercell signal wirings 6 are achieved by the use of the intercell signal wiring exclusive region 4 provided on the outside of the cells. Hence, there has been a problem that a semiconductor integrated circuit device produced by the conventional method in accordance with the standard cell system cannot be improved in an integration degree.